The integrated circuit (IC) industry is attempting to create integrated circuits (ICs) having embedded-DRAM on-chip with metal-oxide-semiconductor (MOS) logic circuitry. However, conventional CMOS logic processing, which uses tungsten (W) and/or polysilicon conductive plugs, is not readily integratable with ferroelectric embedded DRAM processing. Specifically, ferroelectric materials require an oxygen anneal process and/or an oxygen environment deposition process in order to improve the dielectric properties of the ferroelectric capacitor. This deposition or anneal process can adversely oxidize underlying/exposed tungsten and polysilicon plugs which are formed as contacts to MOS DRAM and logic transistors. Due to this oxidation problem, additional processing steps and structures are added to the process flow in an attempt to avoid this adverse plug oxidation.
Furthermore, lower capacitor electrodes of embedded DRAM capacitors are typically reactive ion etched (RIE) resulting in the formation of reactive ion-etched bottom capacitor electrode sidewalls. The reactive ion etch (RIE) of this bottom capacitor electrode roughens the surface of these sidewalls, thereby creating unwanted leakage current in the capacitor device between these sidewalls and an overlying capacitor electrode. A need exists in the IC industry to reduce or eliminate both the plug oxidation problem and the sidewall leakage current problem associated with embedded ferroelectric DRAM technology.
Specifically, the two problems discussed above (i.e., plug oxidation and sidewall capacitor current leakage) are graphically illustrated in the prior art FIG. 1. FIG. 1 illustrates tungsten plugs or polysilicon plug regions 214 as illustrated in FIG. 1. These plugs are formed to a minimum lithographic dimension W1 (roughly 0.25 microns by current standards). However, any exposed portions of the tungsten (W) or polysilicon plug 214 will be readily oxidized in an oxidation environment. In an attempt to prevent plug oxidation, an oxidation barrier layer 215 is formed overlying the contact plug 214
As illustrates that the barrier layer 215 surrounds a periphery of the contact plug by dimension W2. The ferroelectric layer 218 is annealed, or oxygen-environment deposited, to improve the dielectric properties of the ferroelectric material. The oxygen atoms in this temperature-elevated environment may diffuse through the ferroelectric layer 218 and may traverse the distance W2 in layers 215/212 to oxidize the plug 214. As the lithographic feature size W1 and cell size of the DRAM cell of FIG. 1 continues to shrink over time, this dimension W2 will also reduce in size. In addition, the distance W2 can be reduced by lithographic misalignment which is present in all lithographic processing. If the dimension W2, through lithographic misalignment or through cell shrinkage, becomes less than a threshold value, oxygen will be able to readily diffuse through the distance W2 and begin to oxidize upper comers of the tungsten (W) or polysilicon plug 214. This oxidation adversely effects contact resistance of the plug 214 and also adds parasitic interfacial capacitance to the DRAM storage node which compromises the operation of the DRAM cell.
A top capacitor electrode 220 is then formed, after oxygen annealing of layer 218, and lithographically patterned and etched along with the capacitor dielectric 218 as illustrated in FIG. 1. Note that FIG. 1 illustrates a bottom electrode sidewall 219. This sidewall 219 has been created by reactive ion etching (RIE) of the lower capacitor electrode whereby this sidewall 219 has been roughened by the reactive ion etch (RIE) process. Due to the presence of this rough sidewall surface 219 in the capacitor structure, unwanted leakage current will occur between the sidewall 219 and the upper electrode 220. It would be advantageous to reduce or eliminate this sidewall leakage current effect.
Therefore, a need exists in the industry for an embedded DRAM capacitor cell which: (1) prevents the formation of parasitic interfacial capacitance and prevents increased plug contact resistance by avoiding or reducing unwanted plug oxidation; and (2) reduces sidewall leakage current due to RIE etching of a bottom capacitor electrode.